The present invention concerns an improvement in state machine architecture and other devices, the improvement provides for half clock cycle output resolution while retaining full clock cycle internal logic delays.
In a typical state machine the state logic is logically followed by a clocked register. The clocked register, or output register, typically consists of a D flip-flop for each output of the state logic. Output of the clocked register is used both for output of the state machine and a feedback into the state logic. Based on the feedback and on external control inputs, the state logic generates a new set of outputs.
When designing the state logic it is important to take into account propagation delay of signals travelling through the state logic. In general, there needs to be enough time between clock signals so that inputs to the clocked register are settled before each clock signal.
Each clock signal has a rising edge and a falling edge. Generally, the rising edge and falling edge are separated by a period of time equivalent to one half of the total clock cycle. Sometimes it is desirable to have the output register operate on a different clock edge than the clock edge on which the external control inputs are clocked. For example, this may be used to assure that a device controlled by the state machine does not attempt to read output from the output register of the state machine when the output register is in transition.
The simplest method to have the output register operate on a different clock edge than the clock edge on which the external control inputs are clocked is to clock the output register on a different clock edge than the clock edge on which the external control inputs are clocked. In order to do this, however, the system must be designed so that signals are propagated through the state logic within one half of a clock cycle. Propagation delay, as a percentage of clock cycle, may be decreased in a number of ways. For example, the clock cycle can be lengthened. Alternately, the complexity of the state logic may be reduced, i.e., by reducing the number of components through which a signal needs to travel from the input of the state logic to the output of the state logic. Finally, the state logic may be implemented using faster components, reducing the total propagation delay of a signal by reducing the amount of delay in each component through which it travels.
Another method to have the output register operate on a different clock edge than the clock edge on which the external control inputs are clocked is to clock the output register on a different clock edge than the clock edge on which the external control inputs are clocked, but to only clock the output register on every other clock cycle. In this case, however, adjustments need to be made to the external control inputs to assure that the values are held long enough for the output of the state logic to be clocked into the output register.
The above-described prior art methods for having the output register operate on a different clock edge than the clock edge on which the external control inputs are clocked are effective, but can often result in a decrease in system performance or an increase in system manufacturing cost.